1. Field of the Invention
This invention relates to a memory controller for controlling memory within a computer and, more particularly, to a memory controller which dynamically enables/disables memory paging depending on the page hit to precharge ratio for accesses to the memory.
2. Description of the Related Art
A conventional modem computer system includes at least one central processing unit (CPU) located on a CPU (host or local) bus, a mezzanine of peripheral buses, a graphics device coupled to either the CPU or peripheral bus, system memory, and a memory controller for communicating memory access requests from CPU bus and peripheral bus devices to the system memory. Coupled between the various busses are bus interface units. According to somewhat known terminology, the bus interface unit coupled between the CPU bus and a first peripheral bus, such as a PCI bus, is often termed the "north bridge". Similarly, the bus interface unit between the PCI bus and a second peripheral bus is often termed the "south bridge". Typically, the memory controller is a separate integrated circuit device connected to the CPU bus and the system memory. The memory controller receives memory access requests from, e.g., the PCI bus, a graphics port (e.g., AGP), 1394, etc., and/or the CPU. A memory access request includes address and read/write information. The memory controller satisfies memory access requests by asserting the appropriate control signals to the system memory. For DRAM-type memory, these control signals may include address signals, row address strobe (RAS), column address strobe (CAS), and memory write enable (MWE).
The system memory is typically comprised of random access memory (RAM) cells. One type of RAM typically used for main memory in modern computer systems is dynamic random access memory (DRAM). DRAM is organized as an array including rows and columns of memory cells where one bit is stored in a cell. A number of DRAM arrays are combined in parallel to form a word width, and a word is accessed by providing a row address and column address to the DRAM. Normally, the row address and column address are multiplexed on the same signals to obtain a smaller more cost effective structure. The row address is latched in the DRAM by a row address strobe (RAS) and the column address is latched by a column address strobe (CAS). A given row and column address selects a word location to be read or written. To strobe in an address, the RAS or CAS signal is asserted when the corresponding address is valid on the memory address signals. The faster address information may be strobed into the DRAM, the faster the memory may be accessed. However, DRAM devices have specified minimum timing requirements that limit how fast memory accesses may be performed. For example, after RAS is asserted to strobe-in a row address, RAS must then be unasserted for a specified amount of time called the RAS precharge time.
Larger memory systems have multiple banks of DRAM having separate RAS and CAS signals to distinguish between banks. The DRAM forming each bank is often grouped on single in-line memory modules (SIMMs). Various sizes and organizations of SIMMs are often employed. Other structures, such as dual in-line memory modules (DIMMs) are also employed.
Throughput to the system memory is one of the most important factors for determining system performance. Several techniques exist to improve memory throughput. One such technique is interleaving. Interleaving involves sequencing between multiple memory banks so that one bank is accessed during the CAS precharge time for another bank. In this manner, memory accesses are not delayed by waiting for the precharge time.
Another technique used to improve memory throughput is called paging. A page may be defined as an area in a memory bank accessed by a given row address. A page is "opened" when a given row address is strobed in. If a series of access are all to the same page, then once the page is open, only column addresses need be strobed in to the memory bank. Thus, the RAS precharge time is saved for each subsequent access to the open page. Therefore, paging involves leaving a memory page open as long as accesses continue to "hit" within that page. Once an access "misses" the page, the old page is closed and a new page is opened. Opening a new page may incur a precharge time, since only one page may typically be open within a memory bank. If the new page is in the same memory bank, RAS must be precharged before a new page may be opened. If the new page is in a different bank, then the RAS precharge time may already be satisfied for that bank, avoiding an additional precharge delay.
Paging provides the greatest performance enhancement when memory request are frequently page hits. Typically, applications that accesses memory addresses sequentially will benefit from paging the most, because they will have a high page hit ratio. However, some applications result in more random memory accesses and therefore have a lower page hit ratio. If an application has a poor page hit ratio, the memory controller may have to frequently be switching to new pages. Every time a new page is opened in the same bank, a precharge delay will be incurred. If the page hit ratio is poor, paging may actually decrease performance because of this additional precharge delay.
Therefore, it is desirable to have a memory controller that improves system memory throughput. It would be desirable to have a memory controller that performs paging when paging is advantageous, and does not perform paging when no paging is more advantageous. It is further desirable to have a memory controller that continually monitors access patterns to determine when paging is advantageous and modifies paging operation accordingly.